marcel/Ryujinx
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

T32: Implement ALU (shifted register) instructions (#3135)

Browse Source 
* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)

* OpCodeTable: Sort T32 list

* Tests: Rename RandomTestCase to PrecomputedThumbTestCase

* T32: Tests for AluRsImm instructions

* fix nit

* fix nit 2
This commit is contained in:
merry
2022-02-22 22:11:28 +00:00
committed by GitHub
parent 0a24aa6af2
commit 7b35ebc64a
11 changed files with 758 additions and 144 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
ARMeilleure/Decoders/OpCodeT32.cs Normal file
View File

@ -0,0 +1,14 @@
namespace ARMeilleure.Decoders
{
class OpCodeT32 : OpCode32
{
public new static OpCode Create(InstDescriptor inst, ulong address, int opCode) => new OpCodeT32(inst, address, opCode);
public OpCodeT32(InstDescriptor inst, ulong address, int opCode) : base(inst, address, opCode)
{
Cond = Condition.Al;
OpCodeSizeInBytes = 4;
}
}
}