T32: Implement ALU (shifted register) instructions (#3135)

* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)

* OpCodeTable: Sort T32 list

* Tests: Rename RandomTestCase to PrecomputedThumbTestCase

* T32: Tests for AluRsImm instructions

* fix nit

* fix nit 2

Ryujinx.Tests/Cpu/CpuTest32.cs

@@ -257,6 +257,38 @@ namespace Ryujinx.Tests.Cpu
             return GetContext();
         }
 
+        public void RunPrecomputedTestCase(PrecomputedThumbTestCase test)
+        {
+            foreach (ushort instruction in test.Instructions)
+            {
+                ThumbOpcode(instruction);
+            }
+
+            for (int i = 0; i < 15; i++)
+            {
+                GetContext().SetX(i, test.StartRegs[i]);
+            }
+
+            uint startCpsr = test.StartRegs[15];
+            for (int i = 0; i < 32; i++)
+            {
+                GetContext().SetPstateFlag((PState)i, (startCpsr & (1u << i)) != 0);
+            }
+
+            ExecuteOpcodes(runUnicorn: false);
+
+            for (int i = 0; i < 15; i++)
+            {
+                Assert.That(GetContext().GetX(i), Is.EqualTo(test.FinalRegs[i]));
+            }
+
+            uint finalCpsr = test.FinalRegs[15];
+            for (int i = 0; i < 32; i++)
+            {
+                Assert.That(GetContext().GetPstateFlag((PState)i), Is.EqualTo((finalCpsr & (1u << i)) != 0));
+            }
+        }
+
         protected void SetWorkingMemory(uint offset, byte[] data)
         {
             _memory.Write(DataBaseAddress + offset, data);