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Add EXT, CMTST (vector) and UMULL (vector) instructions

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This commit is contained in:
gdkchan
2018-03-02 19:21:54 -03:00
parent 1d71e33171
commit f39a864050
5 changed files with 86 additions and 0 deletions
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5
ChocolArm64/Instruction/AInstEmitSimdArithmetic.cs
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@@ -406,5 +406,10 @@ namespace ChocolArm64.Instruction
{
EmitVectorWidenRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Add));
}
public static void Umull_V(AILEmitterCtx Context)
{
EmitVectorWidenRnRmBinaryOpZx(Context, () => Context.Emit(OpCodes.Mul));
}
}
}

39
ChocolArm64/Instruction/AInstEmitSimdCmp.cs
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@@ -46,6 +46,45 @@ namespace ChocolArm64.Instruction
EmitVectorCmp(Context, OpCodes.Blt_S);
}
public static void Cmtst_V(AILEmitterCtx Context)
{
AOpCodeSimdReg Op = (AOpCodeSimdReg)Context.CurrOp;
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
ulong SzMask = ulong.MaxValue >> (64 - (8 << Op.Size));
for (int Index = 0; Index < (Bytes >> Op.Size); Index++)
{
EmitVectorExtractZx(Context, Op.Rn, Index, Op.Size);
EmitVectorExtractZx(Context, Op.Rm, Index, Op.Size);
AILLabel LblTrue = new AILLabel();
AILLabel LblEnd = new AILLabel();
Context.Emit(OpCodes.And);
Context.EmitLdc_I4(0);
Context.Emit(OpCodes.Bne_Un_S, LblTrue);
EmitVectorInsert(Context, Op.Rd, Index, Op.Size, 0);
Context.Emit(OpCodes.Br_S, LblEnd);
Context.MarkLabel(LblTrue);
EmitVectorInsert(Context, Op.Rd, Index, Op.Size, (long)SzMask);
Context.MarkLabel(LblEnd);
}
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
public static void Fccmp_S(AILEmitterCtx Context)
{
AOpCodeSimdFcond Op = (AOpCodeSimdFcond)Context.CurrOp;

25
ChocolArm64/Instruction/AInstEmitSimdMove.cs
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@@ -57,6 +57,31 @@ namespace ChocolArm64.Instruction
}
}
public static void Ext_V(AILEmitterCtx Context)
{
AOpCodeSimdExt Op = (AOpCodeSimdExt)Context.CurrOp;
int Bytes = Context.CurrOp.GetBitsCount() >> 3;
for (int Index = 0; Index < Bytes; Index++)
{
int Position = Op.Imm4 + Index;
int Reg = Position < Bytes ? Op.Rn : Op.Rm;
Position &= Bytes - 1;
EmitVectorExtractZx(Context, Reg, Position, 0);
EmitVectorInsert(Context, Op.Rd, Index, 0);
}
if (Op.RegisterSize == ARegisterSize.SIMD64)
{
EmitVectorZeroUpper(Context, Op.Rd);
}
}
public static void Fcsel_S(AILEmitterCtx Context)
{
AOpCodeSimdFcond Op = (AOpCodeSimdFcond)Context.CurrOp;