merry bb2f9df0a1 KThread: Fix GetPsr mask (#3180) ...

* ExecutionContext: GetPstate / SetPstate

* Put it in NativeContext

* KThread: Fix GetPsr mask

* ExecutionContext: Turn methods into Pstate property

* Address nit

2022-03-11 03:16:32 +01:00

..

CpuTest32.cs

KThread: Fix GetPsr mask (#3180)

2022-03-11 03:16:32 +01:00

CpuTest.cs

Add multi-level function table (#2228)

2021-05-29 18:06:28 -03:00

CpuTestAlu32.cs

ARMeilleure: A32: Implement SHSUB8 and UHSUB8 (#3089)

2022-02-08 10:46:42 +01:00

CpuTestAlu.cs

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CpuTestAluBinary32.cs

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CpuTestAluBinary.cs

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CpuTestAluImm32.cs

A32: Fix ALU immediate instructions (#3179)

2022-03-05 15:23:10 -03:00

CpuTestAluImm.cs

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CpuTestAluRs32.cs

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CpuTestAluRs.cs

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CpuTestAluRx.cs

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CpuTestBf32.cs

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CpuTestBfm.cs

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CpuTestCcmpImm.cs

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CpuTestCcmpReg.cs

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CpuTestCsel.cs

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CpuTestMisc32.cs

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CpuTestMisc.cs

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CpuTestMov.cs

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CpuTestMul32.cs

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CpuTestMul.cs

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CpuTestSimd32.cs

Implement VCNT instruction (#1963)

2021-02-22 16:26:13 +01:00

CpuTestSimd.cs

CPU - Implement FCVTMS (Vector) (#2937)

2022-01-04 16:45:28 -03:00

CpuTestSimdCrypto32.cs

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CpuTestSimdCrypto.cs

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CpuTestSimdCvt32.cs

Fix Vnmls_S fast path (F64: losing input d value). Fix Vnmla_S & Vnmls_S slow paths (using fused inst.s). Fix Vfma_V slow path not using StandardFPSCRValue(). (#1775)

2020-12-17 20:43:41 +01:00

CpuTestSimdCvt.cs

Implement FCVTNS (Scalar GP) (#2953)

2022-01-19 22:21:44 -03:00

CpuTestSimdExt.cs

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CpuTestSimdFcond.cs

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CpuTestSimdFmov.cs

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CpuTestSimdImm.cs

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CpuTestSimdIns.cs

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CpuTestSimdLogical32.cs

Implement VORN (register) Arm32 instruction (#2396)

2021-06-23 23:21:23 +02:00

CpuTestSimdMemory32.cs

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CpuTestSimdMov32.cs

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CpuTestSimdReg32.cs

CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)

2021-01-04 23:45:54 +01:00

CpuTestSimdReg.cs

CPU (A64): Add Pmull_V Inst. with Clmul fast path for the "1/2D -> 1Q" variant & Sse fast path and slow path for both the "8/16B -> 8H" and "1/2D -> 1Q" variants; with Test. (#1817)

2021-01-04 23:45:54 +01:00

CpuTestSimdRegElem32.cs

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CpuTestSimdRegElem.cs

Add Sqdmulh_Ve & Sqrdmulh_Ve Inst.s with Tests. (#2139)

2021-03-25 23:33:32 +01:00

CpuTestSimdRegElemF.cs

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CpuTestSimdShImm32.cs

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CpuTestSimdShImm.cs

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CpuTestSimdTbl.cs

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CpuTestSystem.cs

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CpuTestT32Alu.cs

T32: Implement Data Processing (Modified Immediate) instructions (#3178)

2022-03-06 22:25:01 +01:00

CpuTestT32Flow.cs

T32: Implement B, B.cond, BL, BLX (#3155)

2022-03-04 23:05:08 +01:00

CpuTestThumb.cs

T32: Implement ALU (shifted register) instructions (#3135)

2022-02-22 19:11:28 -03:00

PrecomputedThumbTestCase.cs

T32: Implement ALU (shifted register) instructions (#3135)

2022-02-22 19:11:28 -03:00