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Implement a new JIT for Arm devices (#6057)

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* Implement a new JIT for Arm devices

* Auto-format

* Make a lot of Assembler members read-only

* More read-only

* Fix more warnings

* ObjectDisposedException.ThrowIf

* New JIT cache for platforms that enforce W^X, currently unused

* Remove unused using

* Fix assert

* Pass memory manager type around

* Safe memory manager mode support + other improvements

* Actual safe memory manager mode masking support

* PR feedback
This commit is contained in:
gdkchan
2024-01-20 11:11:28 -03:00
committed by GitHub
parent 331c07807f
commit 427b7d06b5
135 changed files with 43322 additions and 24 deletions
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103
src/Ryujinx.Cpu/LightningJit/Arm32/Target/Arm64/InstEmitBit.cs Normal file
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using Ryujinx.Cpu.LightningJit.CodeGen;
namespace Ryujinx.Cpu.LightningJit.Arm32.Target.Arm64
{
static class InstEmitBit
{
public static void Bfc(CodeGenContext context, uint rd, uint lsb, uint msb)
{
// This is documented as "unpredictable".
if (msb < lsb)
{
return;
}
Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
context.Arm64Assembler.Bfc(rdOperand, (int)lsb, (int)(msb - lsb + 1));
}
public static void Bfi(CodeGenContext context, uint rd, uint rn, uint lsb, uint msb)
{
// This is documented as "unpredictable".
if (msb < lsb)
{
return;
}
Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
Operand rnOperand = InstEmitCommon.GetInputGpr(context, rn);
context.Arm64Assembler.Bfi(rdOperand, rnOperand, (int)lsb, (int)(msb - lsb + 1));
}
public static void Clz(CodeGenContext context, uint rd, uint rm)
{
Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
context.Arm64Assembler.Clz(rdOperand, rmOperand);
}
public static void Rbit(CodeGenContext context, uint rd, uint rm)
{
Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
context.Arm64Assembler.Rbit(rdOperand, rmOperand);
}
public static void Rev(CodeGenContext context, uint rd, uint rm)
{
Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
context.Arm64Assembler.Rev(rdOperand, rmOperand);
}
public static void Rev16(CodeGenContext context, uint rd, uint rm)
{
Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
context.Arm64Assembler.Rev16(rdOperand, rmOperand);
}
public static void Revsh(CodeGenContext context, uint rd, uint rm)
{
Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
Operand rmOperand = InstEmitCommon.GetInputGpr(context, rm);
context.Arm64Assembler.Rev16(rdOperand, rmOperand);
context.Arm64Assembler.Sxth(rdOperand, rdOperand);
}
public static void Sbfx(CodeGenContext context, uint rd, uint rn, uint lsb, uint widthMinus1)
{
// This is documented as "unpredictable".
if (lsb + widthMinus1 > 31)
{
return;
}
Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
Operand rnOperand = InstEmitCommon.GetInputGpr(context, rn);
context.Arm64Assembler.Sbfx(rdOperand, rnOperand, (int)lsb, (int)widthMinus1 + 1);
}
public static void Ubfx(CodeGenContext context, uint rd, uint rn, uint lsb, uint widthMinus1)
{
// This is documented as "unpredictable".
if (lsb + widthMinus1 > 31)
{
return;
}
Operand rdOperand = InstEmitCommon.GetOutputGpr(context, rd);
Operand rnOperand = InstEmitCommon.GetInputGpr(context, rn);
context.Arm64Assembler.Ubfx(rdOperand, rnOperand, (int)lsb, (int)widthMinus1 + 1);
}
}
}