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T32: Implement ALU (shifted register) instructions (#3135)

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* T32: Implement ADC, ADD, AND, BIC, CMN, CMP, EOR, MOV, MVN, ORN, ORR, RSB, SBC, SUB, TEQ, TST (shifted register)

* OpCodeTable: Sort T32 list

* Tests: Rename RandomTestCase to PrecomputedThumbTestCase

* T32: Tests for AluRsImm instructions

* fix nit

* fix nit 2
This commit is contained in:
merry
2022-02-22 22:11:28 +00:00
committed by GitHub
parent 0a24aa6af2
commit 7b35ebc64a
11 changed files with 758 additions and 144 deletions
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9
Ryujinx.Tests/Cpu/PrecomputedThumbTestCase.cs Normal file
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@@ -0,0 +1,9 @@
namespace Ryujinx.Tests.Cpu
{
public class PrecomputedThumbTestCase
{
public ushort[] Instructions;
public uint[] StartRegs;
public uint[] FinalRegs;
}
}