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[Ryujinx.Tests] Address dotnet-format issues (#5389)

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* dotnet format style --severity info

Some changes were manually reverted.

* dotnet format analyzers --serverity info

Some changes have been minimally adapted.

* Restore a few unused methods and variables

* Fix new dotnet-format issues after rebase

* Address review comments

* Address most dotnet format whitespace warnings

* Apply dotnet format whitespace formatting

A few of them have been manually reverted and the corresponding warning was silenced

* Format if-blocks correctly

* Run dotnet format after rebase and remove unused usings

- analyzers
- style
- whitespace

* Add comments to disabled warnings

* Simplify properties and array initialization, Use const when possible, Remove trailing commas

* cpu tests: Disable CA2211 for CodeBaseAddress and DataBaseAddress

* Revert "Simplify properties and array initialization, Use const when possible, Remove trailing commas"

This reverts commit 9462e4136c0a2100dc28b20cf9542e06790aa67e.

* dotnet format whitespace after rebase

* Apply suggestions from code review

Co-authored-by: Ac_K <Acoustik666@gmail.com>

* First dotnet format pass

* Fix naming rule violations

* Remove naming rule violation exceptions

* Fix comment style

* Use targeted new

* Remove redundant code

* Remove comment alignment

* Remove naming rule exceptions

* Add trailing commas

* Use nameof expression

* Reformat to add remaining trailing commas

---------

Co-authored-by: Ac_K <Acoustik666@gmail.com>
This commit is contained in:
TSRBerry
2023-07-01 04:14:34 +02:00
committed by GitHub
parent 6e28a4dd13
commit e9848339dd
62 changed files with 2263 additions and 1929 deletions
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56
src/Ryujinx.Tests/Cpu/CpuTestAlu.cs
View File

@@ -10,7 +10,7 @@ namespace Ryujinx.Tests.Cpu
{
#if Alu
#region "Helper methods"
#region "Helper methods"
private static uint GenLeadingSignsMinus32(int cnt) // 0 <= cnt <= 31
{
return ~GenLeadingZeros32(cnt + 1);
@@ -33,29 +33,43 @@ namespace Ryujinx.Tests.Cpu
private static uint GenLeadingZeros32(int cnt) // 0 <= cnt <= 32
{
if (cnt == 32) return 0u;
if (cnt == 31) return 1u;
if (cnt == 32)
{
return 0u;
}
uint rnd = TestContext.CurrentContext.Random.NextUInt();
int mask = int.MinValue;
if (cnt == 31)
{
return 1u;
}
uint rnd = TestContext.CurrentContext.Random.NextUInt();
int mask = int.MinValue;
return (rnd >> (cnt + 1)) | ((uint)mask >> cnt);
}
private static ulong GenLeadingZeros64(int cnt) // 0 <= cnt <= 64
{
if (cnt == 64) return 0ul;
if (cnt == 63) return 1ul;
if (cnt == 64)
{
return 0ul;
}
ulong rnd = TestContext.CurrentContext.Random.NextULong();
long mask = long.MinValue;
if (cnt == 63)
{
return 1ul;
}
ulong rnd = TestContext.CurrentContext.Random.NextULong();
long mask = long.MinValue;
return (rnd >> (cnt + 1)) | ((ulong)mask >> cnt);
}
#endregion
#endregion
#region "ValueSource (Types)"
private static IEnumerable<ulong> _GenLeadingSignsX_()
#region "ValueSource (Types)"
private static IEnumerable<ulong> GenLeadingSignsX()
{
for (int cnt = 0; cnt <= 63; cnt++)
{
@@ -64,7 +78,7 @@ namespace Ryujinx.Tests.Cpu
}
}
private static IEnumerable<uint> _GenLeadingSignsW_()
private static IEnumerable<uint> GenLeadingSignsW()
{
for (int cnt = 0; cnt <= 31; cnt++)
{
@@ -73,7 +87,7 @@ namespace Ryujinx.Tests.Cpu
}
}
private static IEnumerable<ulong> _GenLeadingZerosX_()
private static IEnumerable<ulong> GenLeadingZerosX()
{
for (int cnt = 0; cnt <= 64; cnt++)
{
@@ -81,19 +95,19 @@ namespace Ryujinx.Tests.Cpu
}
}
private static IEnumerable<uint> _GenLeadingZerosW_()
private static IEnumerable<uint> GenLeadingZerosW()
{
for (int cnt = 0; cnt <= 32; cnt++)
{
yield return GenLeadingZeros32(cnt);
}
}
#endregion
#endregion
[Test, Pairwise, Description("CLS <Xd>, <Xn>")]
public void Cls_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource(nameof(_GenLeadingSignsX_))] ulong xn)
[ValueSource(nameof(GenLeadingSignsX))] ulong xn)
{
uint opcode = 0xDAC01400; // CLS X0, X0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -108,7 +122,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLS <Wd>, <Wn>")]
public void Cls_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource(nameof(_GenLeadingSignsW_))] uint wn)
[ValueSource(nameof(GenLeadingSignsW))] uint wn)
{
uint opcode = 0x5AC01400; // CLS W0, W0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -123,7 +137,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLZ <Xd>, <Xn>")]
public void Clz_64bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource(nameof(_GenLeadingZerosX_))] ulong xn)
[ValueSource(nameof(GenLeadingZerosX))] ulong xn)
{
uint opcode = 0xDAC01000; // CLZ X0, X0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -138,7 +152,7 @@ namespace Ryujinx.Tests.Cpu
[Test, Pairwise, Description("CLZ <Wd>, <Wn>")]
public void Clz_32bit([Values(0u, 31u)] uint rd,
[Values(1u, 31u)] uint rn,
[ValueSource(nameof(_GenLeadingZerosW_))] uint wn)
[ValueSource(nameof(GenLeadingZerosW))] uint wn)
{
uint opcode = 0x5AC01000; // CLZ W0, W0
opcode |= ((rn & 31) << 5) | ((rd & 31) << 0);
@@ -263,4 +277,4 @@ namespace Ryujinx.Tests.Cpu
}
#endif
}
}
}